1. Field of the Invention
This invention is generally directed to non-volatile memory arrays (e.g. EPROMs) and more particularly to memory arrays having plural memory cells, wherein each cell comprises an asymmetrical split gate structure including a fully insulated floating gate which can be charged to a programmed state by injection of hot electrons through an insulator and an electrically accessible control gate which can be used to address the memory cell. The invention is more specifically directed to a structure and/or method for improving the packing density and/or manufacturing yield of such a memory array.
2. Description of the Related Art
Co-pending application Ser. No. 06/762,582, discloses a memory array having a virtual ground structure. In such a structure, a plurality of elongated conductive semiconductor regions referred to as bit lines are formed integrally in a semiconductor substrate so as to each have opposed first and second edge portions. The opposed edge portions of each bit line respectively function as the drain of a first split gate transistor and as the source of a laterally adjacent second split gate transistor. The structure and operating characteristics of the split gate transistor are described in U.S. Pat. No. 4,409,723 issued to E. Harari Oct. 13, 1983. The contents of U.S. Pat. No. 4,409,723 are incorporated herein by reference.
While the virtual ground structure provides an advantageous arrangement for packing a large number of memory cells into the limited area of an integrated circuit chip and for manufacturing such chips on a mass production basis, it has its limitations. One object of the present invention is to provide a structural layout which enables designers to overcome packing density limitations of the virtual ground structure disclosed in Ser. No. 06/762,582. An appreciation of the interplay between functional components of the virtual ground structure and the manufacturing steps employed to form them will facilitate understanding of how the packing density limitations arise and how the invention overcomes them.
FIG. 1 is a schematic diagram of a memory array 10 having a virtual ground structure such as one described in the above cited application Ser. No. 06/762,582. Briefly, the memory array 10 is integrally formed on a semiconductive substrate 15 (FIG. 3) so as to include a relatively large number (j times k) of split gate transistors Q.sub.11, Q.sub.12, Q.sub.13, . . . Q.sub.jk, arranged in linear rows and columns thereby forming a rectangular matrix. Diffused in the substrate 15 are large number of bit lines, BL.sub.1, BL.sub.2, BL.sub.3, . . . , BL.sub.k+1, where the number k is an integer which by way of example, may be equal to a power of two such as 256, 512, 1024 or 2048. The bit lines are composed of a conductive semiconductor material such as heavily doped N type silicon. Each bit line is elongated to extend across the substrate in a longitudinal direction (y direction). Plural bit lines are repeated at a predetermined first pitch P.sub.BL in the lateral direction (x direction) across the surface of the substrate 15. Portions denoted as D and S at opposed left and right edges, 11 and 12, of each of bit lines BL.sub.2 through BL.sub.k respectively serve as drain and source regions of transistors Q.sub.11 -Q.sub.jk.
The array 10 is further configured to have a large number of conductive word lines, WL.sub.1, WL.sub.2, . . . , WL.sub.j, repeated across the surface of the substrate 15 at a predetermined pitch P.sub.WL in the y direction. (The value j is an integer which, by way of example, may equal a multiple of two such as 256, 512, 1024 or 2048.) The word lines are preferably heavily doped strips of polycrystalline silicon that are disposed to insulatively overlap both the bit lines BL.sub.1 through BL.sub.k+1 and portions of the substrate surface between the bit lines. The word lines WL.sub.1 -WL.sub.j extend orthogonally over the bit lines BL.sub.1 -BL.sub.k+1 such that each word line WL.sub.i of a row i (i being an integer in the range 1 .ltoreq.i.ltoreq.j) defines and interconnects control gate portions 14 of a set of transistors Q.sub.il -Q.sub.ik lying in the same row i to a corresponding node N.sub.Xi of an X-address unit 18. The X-address unit 18 selectively activates an individual one of the word lines WL.sub.1 -WL.sub.j to thereby address a unique row of transistors (memory cells) in the memory array 10 during reading or programming of the array.
The packing density of the array 10 is set once the bit line and word line pitch values, P.sub.BL and P.sub.WL, are selected. The x-by-y substrate area A.sub.cell attributed to each cell of the memory array 10 is fixed to the product P.sub.BL P.sub.WL. Those skilled in the art will readily appreciate that this attributed cell area A.sub.cell is a very important factor in the production of integrated circuit chips. It determines how many dies can be packed on each production wafer, the manufacturing yield of the production line, and whether a die of preselected dimensions can be mass produced to have a relatively large memory capacity of, say for example, 1M bits, 4M bits, or even higher (M=1,048,576). These latter factors determine whether or not an IC chip of a specific design will satisfy industry demands for increased memory capacity at lower costs per bit. To satisfy industry demand, it is generally desirable to minimize die area, maximize the number of memory cells on each die and maximize the number of die on each wafer in a manner which concurrently assures that the electrical and mechanical requirements of a prespecified circuit design are met.
The pitch values, P.sub.BL and P.sub.WL, cannot be selected arbitrarily. They are intertwined with both the functional design requirements of the integrated circuit and the miniaturization capabilities of available manufacturing processes. In the configuration of FIG. 1, for example, the bit lines B.sub.L1 -BL.sub.k+1 must be designed to couple the source and drain regions of transistors in adjacent transistor columns to respective contact nodes N.sub.Y1 through N.sub.Y(k+1) of the array 10 in a manner which assures that prespecified source and drain voltage levels will develop at the source and drain regions of the transistors. The contact nodes are vertically oriented vias which connect the diffused bit lines B.sub.L1 -BL.sub.k+1 of the substrate to metal lines ML.sub.1 through ML.sub.k+1 overlying the substrate. The metal lines couple the bit lines to a Y-addressing/programming/sensing unit 20. There is a one-to-one correlation between each of the metal lines and the diffused bit lines, so the metal lines ML.sub.I through ML.sub.k+1 and the bit lines BL.sub.I through BL.sub.k+1 are preferably repeated over the surface of the substrate at the same pitch P.sub.BL.
Unit 20, which will also be referred to as the Y-address unit 20, includes circuitry for switchably setting the voltage of each of the contact nodes, NY.sub.1 -N.sub.Y(k+1), to one of a preselected plurality of voltage levels, including a low voltage V.sub.L, (e.g., ground) an intermediate voltage V.sub.I (e.g., +2 volts) and a high voltage V.sub.H (e.g., +9 volts). The Y-address unit 20 is actuated such that a desired one of the transistors Q.sub.11 -Q.sub.jk can be individually addressed for programming or reading.
Since the bit lines BL.sub.I -BL.sub.k+1 are not perfect electrical conductors but rather impurity doped (N+) semiconductor regions and since semiconductor materials typically have resistivity values much higher than the metal materials normally used to form the metal, lines, ML.sub.1 - ML.sub.k+1, vertical segments of each bit line (we will use bit line BL.sub.k as an example) may be characterized as having nonnegligible segment resistances R.sub.y1, R.sub.y2, R.sub.y3, . . . , R.sub.yj. The resistance value of each segment is proportional to its length and inversely proportional to its width. The total resistance separating contact node N.sub.Yk from the source region S of the transistor, Q.sub.1k, (and incidentally for the purpose of simplification Q.sub.1k will be assumed here to be a transistor that is most distally located in an electrical sense from contact node N.sub.Yk), depends on the sum of the individual segment resistances R.sub.y1 through R.sub.yj of bit line BL.sub.k. The total resistance separating the drain region D of transistor Q.sub.1k from contact node NY.sub.(k+1) similarly depends on the sum of the segment resistances in bit line BL.sub.k+1. Thus, when the Y-address unit 20 switches node N.sub.Yk to the low potential level V.sub.L so that node N.sub.Yk will act as a virtual ground, and switches node N.sub.Y(k+1) to an intermediate or high level (V.sub.I or V.sub.H) so that node N.sub.Y(k+1) will provide a drain potential that enables either the reading or programming of transistor Q.sub.1k, the voltage at the source region S of transistor Q.sub.1k may be higher than a desired virtual ground level (due to a voltage drop generated across the segment resistances of bit line BL.sub.k when a prespecified reading or programming current flows through the bit line) and the voltage at the drain region D of transistor Q.sub.1k may be lower than a desired drain level (due to current flow through the segment resistances of bit line BL.sub.k+1).
Those skilled in the art will, of course, appreciate that it is customary to provide plural contact nodes (vertical vias) at multiple points along the length of each bit line for coupling the bit line to an overlying metal line and minimizing the resistance effects of the diffused bit line. By way of example, bit line BL.sub.k would ordinarily have a number of contact nodes N.sub.1k through N.sub.mk (not shown) distributed along its length, where m is an integer much larger than 2, i.e., m=20. Only one contact node N.sub.Yk is shown along the length of bit line BL.sub.k in FIG. 1 for the sake of simplifying the discussion. It will be understood that in the case of a bit line having plural contact nodes, the transistor regions located approximately midway between adjacent contact nodes of the bit line are usually the ones that are most distal in the electrical sense and suffer most from increased bit line resistance.
Referring still to the structure of FIG. 1, it can be appreciated that if all the transistors, and especially the transistors which are electrically most distal from the contact nodes of each bit line, i.e. Q.sub.1k, are to operate properly, care must be taken to assure that the effective channel width of each transistor is equal to or greater than a minimum effective width W.sub.min necessary for conducting predetermined, minimum read and write currents, I.sub.Rmin and I.sub.Pmin, and further that the summed y-direction resistance values of the bit lines, i.e., BL.sub.k and BL.sub.k+1, are each kept below a design maximum R.sub.Ymax. This means that the effective channel width of each transistor has to be controlled during fabrication to assure it is at least as wide as the minimum width W.sub.min and that the width and length dimensions of segment resistances R.sub.y1, R.sub.y2, . . . R.sub.yj have to be controlled during fabrication so as to assure that the sum of their resistance values will not exceed the design maximum R.sub.Ymax.
This is where the selection of the pitch values, P.sub.BL and P.sub.WL, comes into play. Those skilled in the art will appreciate that precise control of the effective channel widths of densely packed transistors and precise control of the widths of the segment resistances R.sub.y1, R.sub.y2, . . . R.sub.yj is difficult to achieve when integrated circuit chips are manufactured on a mass production scale. As such, integrated circuit designers are constrained in how small they can make the values of the bit line and word line pitches, P.sub.BL and P.sub.WL.
The basis for these constraints can be appreciated better by referring to FIGS. 2A-2C. FIG. 2A is a top plan view of a portion of the memory array 10 of FIG. 1 as it generally appears after lithographic design but before it is actually fabricated into an integrated circuit. FIG. 2B shows an enlarged view of a portion of FIG. 2A. FIG. 2C, shows a portion of the device after fabrication. The discussion will focus mainly on FIG. 2A here. It is sufficient to note for now that with respect to FIGS. 2B and 2C that the shapes in the lithographic layout of FIG. 2A are distorted during fabrication by etch shrinkage, dopant diffusion, oxide growth, and other process mechanisms thereby producing the shapes shown in FIG. 2C.
In FIG. 2A first through third word lines WL.sub.1 -WL.sub.3 are shown crossing over semiconductive (N.sup.+) bit lines BL.sub.1 -BL.sub.3, with parts of an oxide insulation 30 (FIG. 3) and portions of the word lines WL.sub.1 -WL.sub.3 removed to expose lightly doped (P.sup.-) inter-channel regions 15b of the substrate, lightly doped (P.sup.-) channel regions 15c of the substrate, and a rectangular matrix of floating gates FG.sub.11 through FG.sub.33 belonging to respective transistors Q.sub.11 through Q.sub.33. The floating gates FG.sub.11 -FG.sub.33 are insulatively supported above the bit lines by a thin gate oxide layer 30a which may be seen in the cross-sectional views taken along lines 3--3, 4--4, 5--5 and illustrated respectively in FIGS. 3, 4 and 5. Thicker field oxide portions, FO.sub.11 through FO.sub.33, of the oxide insulation 30 are positioned between the floating gates as seen in FIGS. 2A-2C, 4 and 5. FIG. 2A is not drawn entirely to scale. The floating gates FG.sub.12 -FG.sub.33 of bit lines BL.sub.2 and BL.sub.3 are shown to be spaced relatively far apart from their corresponding source sections on respective bit lines BL.sub.1 and BL.sub.2. This large spacing was used to avoid cluttering in the illustration of FIG. 2A. Distances L.sub.p1 and L.sub.p2 are normally of approximately the same size (i.e., L.sub.p1 =1.3 micron and L.sub.p2 =1.1 micron) as is better seen in FIG. 3.
Referring to the cross sectional view of FIG. 3, the thin layer 30a, or gate oxide, (which is preferably composed of silicon dioxide) spaces a control gate portion 14 and a floating gate portion 16 of each transistor closely (approx. 500 .ANG. or less) to the top surface 15a of the semiconductive substrate 15 so as to enable each of the control and floating gate portions, 14 and 16, to control electrical conduction through channel regions 15c of the substrate. The channel regions 15c are located between edge portions, S and D, of bit lines BL.sub.1 -BL.sub.k+1 which are preselected to function as either the source or drain region of a split gate transistor. Referring momentarily to FIG. 4 it should be noted that the bit line edges also have portions X which are not designated to function as either a source or a drain and these portions X will be referred to as nonsource/nondrain portions. Referring back to FIG. 3, respective read and programming currents, I.sub.R and I.sub.P, can, under certain conditions, flow through an inversion layer induced in the channel region 15c of a selected transistor when the control gate 14 of the transistor is activated.
Referring to FIG. 4, the thick field oxide portions FO of the oxide insulation 30 usually have thicknesses of 1000 .ANG. or greater and more typically 5000 .ANG. or greater. These field oxide portions FO are grown to be interposed between nonsource/nondrain portions X of adjacent bit lines, as shown, so as to inhibit leakage current I.sub.x. Such use of the field oxide portions is commonly referred to as oxide isolation.
Referring to FIG. 5, and also to FIGS. 2B and 2C, the field oxide portions FO have a tendency to expand by imprecisely controllable distances in the x and y directions, and generate a "Bird's Beak" condition. By way of example, the Bird's Beak expansion can be on the order of 0.6 micron in a layout which generally follows a 1.2 micron design rule. This can have substantial consequences on the options available to chip designers. When Bird's Beak expansion occurs, respective left and right edge portions 16a, 16b of the floating gates 16 can be lifted away from the substrate by substantial distances, i.e., greater than 200-500 .ANG., so that these edge portions 16a, 16b are prevented from inducing substantial inversion in the underlying substrate 15 even when such inversion is desired. Normally, a relatively small designed-in overlap DO (e.g. 0.1 micron), is desired between the floating gates FG and the field oxide portions FO. The designed-in overlap DO guards against misalignment between a later-to-be-described poly 1 patterning step (that defines the floating gates FG.sub.11 -FG.sub.33) and other patterning steps. If misalignment in the Y-direction is less than the designed-in overlap DO, the thickness of the field oxide portions in the zone of the overlap do inhibit the misalignment from generating a situation wherein an undesirable conductive path might be formed between adjacent bit lines, the undesirable conductive path being one that is activated by a misaligned word line but not controlled by a floating gate. This protection against misalignment induced problems is a beneficial aspect of the field oxide portions, but there is a detrimental aspect as well.
Referring to FIGS. 2B and 2C, lateral growth of the field oxide in the y-direction, beyond the dimension of the designed-in overlap DO (a phenomenon which is difficult to control to a high degree of precision), can reduce the post-fabrication, effective channel width W.sub.p of the transistors. When the effective width W.sub.p of a transistor is reduced below a required design minimum W.sub.min the read current I.sub.R of the transistor (which is a function of the effective channel width under the floating gate I.sub.R =f (W.sub.p)) might diminish below a design minimum I.sub.Rmin and the array 10 may then fail to operate according to specifications. To guard against this, the floating gates are usually drawn to have an overall y-direction dimension, F.sub.yd =2DO+W.sub.d, which is significantly larger than the minimum effective width W.sub.min actually needed for producing the minimum read current I.sub.Rmin. That is, the drawn effective width W.sub.d (FIG. 2B) is chosen to be sufficiently larger than the minimum effective width W.sub.min so that even under worst case expansion of the Bird's Beak (e.g. 0.6 micron beyond each side of the designed-in overlap DO) the post-fabrication effective channel width W.sub.p would still be large enough to allow the minimum read current I.sub.Rmin to flow. (E.g for a preselected W.sub.min of 1.7 microns, the drawn width would be chosen to be W.sub.d =1.7+2(0.6)=2.9 microns.) As a result of this precaution, the word line pitch P.sub.WL, which is determined by the drawn effective width W.sub.d plus twice the designed-in overlap DO plus a separation distance FS that is to be discussed later (P.sub.WL =W.sub.d +2DO+FS), is forced to be significantly larger than would otherwise be necessary. By way of example, in the design of a so called non-staggered virtual ground array having a word line pitch of 4.2 microns, 1.7 microns are assigned for the minimum effective width W.sub.min, 1.2 microns are assigned for Bird's Beak growth, 1.3 microns are consumed by a floating gate separation distance FS to be discussed later, and 0.2 microns are used up by the designed-in overlap DO. From the above, it can be seen that precautions taken against mask misalignment and Bird's Beak expansion cause the attributed area A.sub.cell =P.sub.WL P.sub.BL of each memory cell to be larger than otherwise necessary at least as far as the word line pitch P.sub.WL is concerned.
It may appear that if the attributed cell area A.sub.cell =P.sub.WL P.sub.BL cannot be reduced by decreasing the word line pitch P.sub.WL (because of the above precautions), then perhaps cell area could be reduced by selecting a smaller bit line pitch P.sub.BL. But here again, there are interactions between process related factors including excessive growth of the field oxide, excessive bit line resistance, mask misalignment, and the electrical characteristic requirements of the fabricated transistors which need to be considered. With respect to these factors, it is useful to briefly review how integrated circuits are fabricated in mass production fashion.
In one method of fabricating the memory array 10, the thick field oxide portions FO are grown on the planar surface of a mono-crystalline silicon substrate using a first lithographic pattern or "mask." A first polysilicon layer (poly-1 layer) is formed on the substrate after the field oxide is grown. The poly-1 layer is patterned (e.g., plasma etched) using a second lithographic mask to define floating gates FG.sub.11 -FG.sub.jk as a plurality of linearly arranged rows and columns. The floating gate pattern will have lithographically drawn original x and y dimensions, F.sub.xd and F.sub.yd, (FIG. 2B), but after etching, the floating gate shapes tend to shrink to smaller post-fabrication dimensions F.sub.xp and F.sub.yp as indicated in FIG. 2C. It is worthwhile to note here that etch shrinkage is accentuated at corner portions of the drawn floating gate shapes in comparison to flat side portions of the drawn floating gate shapes and that the corners have a tendency to become rounded as they shrink. It will be seen that the invention takes advantage of this phenomenon. This corner rounding phenomenon may take place regardless of whether the floating gate pattern is defined by photolithographic masking or plasma etch or other patterning techniques.
After the patterning of the floating gates, a photoresist layer is deposited and patterned by a third lithographic mask to have an implant window defined therethrough (refer to FIG. 7A). The photoresist pattern is preferably aligned relative to the floating gates such that the implant window (e.g., 50a of FIG. 7A) has a first window-edge (50a-1) aligned midway between the edges of floating gates in a single column, and an opposed second window-edge (50a-2) which is spaced away from edges of the floating gates in the single column.
Next the bit lines BL.sub.1 -BL.sub.k+1 are ion implanted in a self-aligning manner using bit-line-defining edges (E1 through E4 of FIG. 7A, for example) of the floating gates (FG1 through FG4, for example) and portions of the photoresist (50) in combination as a mask. After the bit line dopants have been implanted, the photoresist (50) is removed, insulation is formed on the surfaces of the floating gates, and the implanted bit line dopants are diffused laterally to extend the bit line shapes under the floating gate edges by a diffusion determined distance L.sub.D as indicated in FIG. 3.
In a later step, the word lines WL.sub.1 -WL.sub.j are formed by depositing a layer of conductive material on the insulation covering the floating gates and patterning this deposited layer with yet a fourth mask. The word lines are preferably composed of heavily doped polysilicon (poly-2 layer), as are the floating gates (poly-1 layer).
Referring to FIGS. 2A-2C, the bit lines BL.sub.1 -BL.sub.k+1 will have a lithographically drawn, x-direction dimensions, B.sub.xd, B.sub.xdo, B.sub.xdf at various portions thereof as shown in FIG. 2B, but because of fabrication factors such as etch shrinkage and lateral dopant diffusion, the bit lines will be distorted in shape and will have different post-fabrication dimensions B.sub.xp, B.sub.xpo, B.sub.xpf as shown in FIG. 2C. It will be noted in comparing FIGS. 2B and 2C that the field oxide portions FO enlarge from drawn x,y dimensions O.sub.xd, O.sub.yd to larger post-fabrication dimensions O.sub.xp, O.sub.yp due to lateral expansion. As a result, the field oxide portions FO affect both the oxide dependent, width dimension, B.sub.xpo, of the bit lines and the post-fabrication effective channel width W.sub.p of the transistors. It should be obvious, incidentally, that some of the features shown in FIG. 2A (i.e. word lines, floating gates and oxide portions) are omitted in FIGS. 2B and 2C so that the changes in bit line, oxide and floating gate shapes can be better seen.
When the bit line pitch P.sub.BL is selected, it must include at least the following two predetermined overlap lengths which determine the electrical characteristics of the transistors: L.sub.p1, which is a predetermined channel length under control of the floating gates; and L.sub.p2, which is a predetermined channel length under control of the control gates (word lines). After these two overlap lengths, the selected bit line pitch P.sub.BL will include a floating gate affected, dimension, B.sub.xdf, of the bit lines plus the expected side diffusion L.sub.D of the bit lines. In a previous nonstaggered virtual ground design having a bit line pitch of 4.2 microns, 1.8 microns of the pitch were consumed by the drawn width B.sub.xd, 1.3 microns by L.sub.p1 and 1.1 microns by L.sub.p2. The values of L.sub.p1 and L.sub.p2 were fixed by certain electrical characteristics desired for the split gate transistors. The value of B.sub.xd, as will be seen in the following detailed discussion, was constrained to some extent by concerns for generating excessive bit line resistances. It was also constrained to some extent by concerns about excessive growth of the field oxide portions FO. Also, the design rules of the metal lines ML generated some constraints.
The resulting attributed cell area A.sub.cell =P.sub.BL P.sub.WL for the exemplary pitch values given above, namely P.sub.BL =4.2 microns and P.sub.WL =4.2 microns, was approximately 17.5 microns.sup.2. The above description seems to indicate that nothing can be done to reduce cell area further unless one is willing to sacrifice electrical performance and/or manufacturing yield. It will be seen from the following that it is possible to reduce cell area even further without sacrificing electrical performance and manufacturing yield.